Dynamic random access memory system with simultaneous access and

Details Dynamic random access memory system with simultaneous access and Dynamic random access memory system with simultaneous access and

1998-05-18

1999-10-05

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Data refresh

365149, 36518904, 365203, G11C 700

Patent

active

059634979

ABSTRACT:
A memory 200 including an array 201 of rows and columns of 2-transistor, 1-capacitor memory cells 301 of the cells of each row coupled to first and second wordlines 303a, 303b and the cells of each column coupled to a pair of bitlines 302a, 302b. Refresh circuitry 208 activates the first wordline 303a plus selected said row and refreshes the cells 301 of that row through a first one of the bitlines 302a of each of the columns. Data access circuitry 202, 204 substantially simultaneously activates the second said wordline 303b of a second selected row and accesses selected cells of the second row through a second one of the bitlines 302b in the corresponding columns.

REFERENCES:
patent: 5007022 (1991-04-01), Leigh
patent: 5010519 (1991-04-01), Yoshimoto et al.
patent: 5381379 (1995-01-01), Fukumoto
patent: 5636174 (1997-06-01), Rao
"Transparent-Refresh DRAM (TreD) Using Dual-Port DRAM Cell" by Sakurai, Nogami, Sawada and Iizuka, 1988 IEEE Custom Integrated Circuits Conference pp. 4.3.1 through 4.3.4.

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