Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
1999-04-20
2001-05-15
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S149000, C365S230060
Reexamination Certificate
active
06233193
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to electronic memories and in particular to a dynamic random access memory with a Static Random Access Memory Interface operations and methods using the same.
BACKGROUND OF THE INVENTION
Dynamic random access memory (DRAM) is the principal type of memory used in most applications such as personal computers (PCS). When compared, for example, to static random access memory (SRAM), DRAM is less expensive, consumes substantially less power, and provides more bits in the same chip space (i.e. has a higher cell density). DRAM is normally used to construct those memory subsystems, such as system memories and display frame buffers, where power conservation and high cell density are more critical than speed. In most computing systems, it is these subsystems which dominate the system architecture, thus making DRAM the prevalent type of memory device on the market.
Notwithstanding these significant advantages, DRAMs are also subject to significant restraints due to the manner in which they must be constructed and operated. Specifically, since each cell stores data as charge on a capacitor (i.e. charged to a predetermined voltage for a logic 1 and discharged to approximately 0 volts for a logic 0), the length of time a bit, and in particular a logic 1 bit, can be stored in a given cell is a function of the ability of the capacitor to retain charge. Charge retention, and consequently data integrity is in turn a function of charge leakage.
For purposes of the present discussion, two particular charge leakage mechanisms will be considered. In the first mechanism, leakage from the capacitor storage plate to plate occurs because the high dielectric layers used to make small capacitors with sufficient capacitance are lossy. Second, charge on the storage plate of the cell leaks back through the pass transistor during the transistor off state (“subthreshold leakage”). In a robust DRAM design, each of these problems must be addressed.
Almost all DRAMs maintain data integrity through the periodic refresh of the memory cells to the voltage of the logic 1 data, which has deteriorated as charge has leaked off the capacitor, back to the full storage voltage. This is done by simply reading and restoring the data in cells in the cell array row by row. Depending on the refresh scheme, all the rows in the array or subarray may be refreshed by stepping though the rows in a single sequence or by distributing the refresh of smaller groups of rows of the array between read and write operations. In any event, refresh can seriously impact the performance of the DRAM. Among other things, refresh consumes memory cycles which would otherwise be available for reads and writes; every refresh of a row requires a new precharge/active cycle. With each cycle used for refresh, the array or subarray containing the row being precharged is unavailable for read and write accesses. The problem of refresh is only compounded as high density devices are contemplated, where the refresh period must be reduced in order to be able to refresh the entire array without reducing the time the system can access the memory.
Efforts have been made to minimize cell leakage such that the integrity of the data can be maintained for a longer period of time and hence the period between required refresh correspondingly increased. One way has been to bias the substrate in which the cells sit to reduce subthreshold leakage. Presently a triple-well process is used. Consider the case of n-channel pass transistors. In the triple-well process, the n-channel pass transistors in the DRAM cell (as well as the storage capacitors) array sit in an isolated p-type well which in turn sits in a n-type well. The n-type well has previously been formed in a p-type substrate. The p-type well in which the cells sit is then biased by a negative voltage V
BB
, which is typically around −1 V, with respect to the grounded substrate. Similarly, Ip-channel pass transistors sit in an isolated n-type well which in turn sits in an s-type well. This effectively raises the threshold voltage of the cell pass transistors and cuts off subthreshold leakage. The separate p-well is used to isolate the array from the peripherals such that the biasing of the cell array does not degrade the performance of the peripheral circuits which have a grounded substrate. Without the isolated p-well, the substrate biasing would also raise the threshold of the transistors in the high performance peripherals and deteriorate their performance.
The triple well process along with the charge pumps which produce the bias voltage V
BB
are difficult and expensive to implement. The ability to eliminate them would provide substantial advantages over the prior art and represent a substantial leap in DRAM technology. Additionally, the elimination of the isolated p-well, and correspondingly the intervening n-well, the fabrication process for the cell array becomes more compatible with that of the remaining circuitry on the chip, particularly the high performance circuitry in the periphery.
As DRAM cell densities increase, cell size, and correspondingly storage capacitor size, must shrink. Capacitor size is a function of the capacitor dielectric material chosen, the higher the dielectric constant of the material, the more capacitance can be achieved per unit area. While high dielectric materials allow for the fabrication of smaller capacitors, such materials, due to their physical nature, are leaky and must be refreshed at a higher rate. On the other hand, lower dielectric materials are less leaky but force the use of larger capacitor plates. As a consequence, trench, stacked and other complex capacitor structures have been developed to allow the use of lower dielectric constant, lower leakage materials, and which consequently increase in capacitor plate size, while still allowing the overall size of the cells to be small.
Thus, the need has arisen for circuits, system and methods which support efficient refresh of DRAM arrays. Such methods circuits, systems and methods should be sufficiently robust such that the triple-well process and the associated charge pumps can be eliminated. Further, the ability to use leaky, high dielectric materials in the construction of smaller memory cells should also be addressed.
SUMMARY OF THE INVENTION
The principles of the present invention are embodied in a memory comprising an array of rows and columns of dynamic memory cells, the cells of each of the rows coupled to an access wordline and a refresh wordline and the cells of each column coupled to an access bitline and refresh bitline. Refresh circuitry refreshes a row of cells using a corresponding refresh wordline and a corresponding refresh bitline. Access circuitry accesses selected cells of a selected row using a corresponding access wordline and a corresponding access bitline. The access circuitry includes a new address detector for detecting receipt of a new address by the memory, a row decoder for selecting the access wordline in response to receipt of the row address, and access sense amplifiers and an access column decoder accessing at least one cell along the selected access wordline using the corresponding access bitline.
The present concepts are also embodied in an information storage device. A plurality of memory cells are organized in rows and columns, with each cell including a first transistor for coupling a storage capacitor of the cell with a first data line of a column of cells in response to a signal applied to a first control line to a row of cells containing the cell and a second transistor for coupling the capacitor with the second data line of the column of cells in response to a signal applied via a second control line to a row of cells containing the cell. The device also includes access circuitry and refresh circuitry. The access circuitry generates the receipt of an access address addressing a cell being accessed, decodes the address to activate the first control line of the row containing the cell being accessed, an
Holland Walland Bart
Seitsinger Stephen
Hoang Huan
Murphy, Esq. James J.
Silicon Aquarius, Inc.
Winstead Sechrest & Minick
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