Dynamic random access memory system including predecoder means

Details Dynamic random access memory system including predecoder means Dynamic random access memory system including predecoder means

1989-07-05

1990-08-21

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

36523008, 365226, G11C 700

Patent

active

049512587

ABSTRACT:
A dynamic random access memory system comprising a memory cell matrix, a row address decoder connected to the memory matrix and a counter for producing internal address signals to refresh the cells of the memory cell matrix. A row address buffer converts the external address signals to row address signals in response to an address buffer enabling signal, and a switching circuit connected to the counter and the row address buffer is selectively switching between the counter and the row address buffer in response to an address switching signal. A decoder circuit connected to the output of the switching circuit decodes selected address signals and provides decoded address signals to the row address decoder. A first control circuit connected to the row address buffer provides the address buffer enabling signal to the row address buffer in response to a row address strobe signal, and a second control circuit provides the address switching signal to the switching circuit in response to the row address strobe signal and a column address strobe signal.

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