Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2001-01-08
2002-06-25
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S230060, C365S226000
Reexamination Certificate
active
06411543
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a dynamic RAM (DRAM), a semiconductor storage device, and a semiconductor IC device and to a technology to be efficiently applied to a memory access scheme to access dynamic memory cells.
BACKGROUND OF THE INVENTION
There is type of a dynamic RAM having a voltage generator circuit including charge pump circuits for producing a back bias voltage to be supplied to a substrate of the RAM and a boosting voltage to generate a selection voltage boosted for a word line of the RAM. JP-A-3-214669 describes an example of such a dynamic RAM. In the dynamic memory described in JP-A-5-291534, the substrate voltage is set to 0 volt (V), the data line has a high-level potential of 2 V and a low-level potential of 1 V, and the word line possesses a selection level of 3 V. In the publication “ISSCC '94/Session 8/DRAMs and Non-Volatile Memories/Paper TA 8.2”, there has been described a boosted sense-ground technology. On the other hand, JP-A-7-57461 is directed to a technology related to a memory array in which the amplitude of the data line voltage is set such that the high and low levels of the data line are respectively set to 1.5 V and 0 V and the amplitude of the word line voltage is selected such that the high and low levels of the word line are respectively set to 2 V V and −0.5 V. In JP-A-5-12866, there has been described a dynamic RAM in which neither a substrate biasing circuit nor a word boosting circuit are employed. JP-A-7-240093 discloses a dynamic RAM in which a memory array including bit lines, a memory cell, and a sense amplifier are supplied with a low-level potential which is higher than the ground potential of the RAM chip.
A dynamic memory cell includes address selecting metal-oxide field-effect transistors (MOSFETs) and an information storing capacitor to achieve information storage according to the presence or absence of an electric charge in the capacitor. To keep information in the form of charge for a long period of time, it is required to supply a negative back bias to a substrate gate (corresponding to a channel region) on which the address selection MOSFETs are fabricated so as to increase the value of the effective threshold voltage of the MOSFETs.
In such MOSFETs which constitute a peripheral circuit to achieve an operation to select an address of the dynamic memory cell and which constitute a sense amplifier and a main amplifier, when a negative back bias voltage is supplied to the substrate gate, the threshold voltage is increased according to the supplied voltage. This leads to reduction in conductance in the on state thereof and hence the operation speed of the circuit is accordingly lowered. To avoid this drawback, there has been proposed a method in which a negative back bias voltage is applied to the memory array section including the dynamic memory cells. However, in such a case in which, for example, different bias voltages are supplied respectively to a substrate of the memory array section and a substrate of the peripheral circuit section, it is required to separate a well region as a substrate of the memory array section and a well region as a substrate of the peripheral circuit section. This disadvantageously complicates the production process of the semiconductor devices.
In a high-level write operation for the dynamic memory cell, since the information storage capacitor is charged up via the address selection MOSFET, it is necessary to set the gate potential of the MOSFET to an appropriate level. When this operation is not conducted, the charge-up level is lowered according to the voltage corresponding to the threshold voltage of the MOSFET, and hence the amount of the information charge is reduced. To prevent such a level reduction, the selection level of the word line connected to the gate of the MOSFET is set to a voltage obtained by adding at least the threshold voltage to the high-level voltage applied to the bit line. As indicated above, in the conventional dynamic RAM, a voltage boosting operation for the word line selection is required. To generate such a boosting voltage for the word lines and the substrate back bias voltage, there are respectively required charge pump circuits. This resultantly leads to a relatively large area increase in current consumoption current, which is a distinct drawback.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a dynamic RAM which capable of an improved degree of circuit integration and an increase in the operation speed without complicating the production process.
Another object of the present invention is to provide a semiconductor IC device including a dynamic RAM in which the degree of circuit integration is improved and the operation speed is increased without complicating the production process.
The above and other objects, as well as other novel features of the present invention, will be more easily understood in conjunction with the following description and accompanying drawings.
In short, the present invention will be representatively described as follows. Namely, there is included a dynamic RAM on a semiconductor substrate and at least a memory control circuit mounted on the substrate. In the dynamic RAM, a first internal voltage is produced to have a voltage difference relative to a power source voltage, the voltage difference being substantially equal to the threshold voltage of the address selection MOSFET in a dynamic memory cell such that the first internal voltage is supplied to the sense amplifier as a high-level operation voltage. A second internal voltage is created to have a predetermined voltage difference relative to the circuit ground potential and is supplied to the sense amplifier as a low-level operation voltage. A write amplifier produces a write signal of which the high and low levels correspond to the first and second internal voltages, respectively. The write signal is transferred to complementary bus lines. On the other hand, a word line connected to the dynamic memory cell receives a word line selection signal or a memory selection signal of which a high level, such as the level of the power source voltage, is set as a selection level and a low level, such as that of the circuit ground potential, is selected as a non-selection level.
REFERENCES:
patent: 5295111 (1994-03-01), Tsujimoto
patent: 3-214669 (1991-09-01), None
patent: 5-12866 (1993-01-01), None
patent: 5-62467 (1993-03-01), None
patent: 5-109274 (1993-04-01), None
patent: 5-128857 (1993-05-01), None
patent: 5-291534 (1993-11-01), None
patent: 6-76574 (1994-03-01), None
patent: 7-57461 (1995-03-01), None
patent: 7-240093 (1995-09-01), None
Aoki et al., “A 1.5K DRAM for Battery-Based Applications”, 1989 IEEE Int'l Solid-State Circuits Conference, pp. 238-239 & 349.
Asakura et al., “A 34ns 256Mb DRAM with Boosted Sense-Ground Scheme”, 1994 IEEE Int'l Solid-State Circuits Conference.
Tsukude et al., “Automatic Voltage-swing Reduction (AVR) Scheme for Ultra Low Power DRAMs”, 1994 Symposium on VLSI Circuits Digest of Technical Papers.
Asakura et al., “An Experimental 256-Mb DRAM with Boosted Sense-Ground Scheme”, Jrnl of Solid-State Circuits, vol. 29, No. 11, Nov. 1994.
Ooishi et al., “An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAMs”, IEEE Journal of Solid-State Circuits, vol. 30, No. 4, Apr. 1995, pp. 471-479.
Aoki Yasunobu
Fujisawa Hiroki
Hasegawa Masatoshi
Kajigaya Kazuhiko
Miyatake Shin-ichi
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