Dynamic random access memory including stress test circuitry

Details Dynamic random access memory including stress test circuitry Dynamic random access memory including stress test circuitry

1991-12-26

1993-10-19

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365203, 365206, G11C 702

Patent

active

052552292

ABSTRACT:
A dynamic random access memory according to the present invention comprises a voltage stress test pad to which a stress voltage is externally applied when a voltage stress test is carried out, transistors which turn off when the stress voltage is not applied to the voltage stress test pad and which, when the stress voltage is applied thereto, transmit the stress voltage to more word lines than those selected in response to an external address signal in a normal operation mode, and a noise killer control circuit for turning off a noise killer circuit connected to a word line to which the stress voltage is applied when the voltage stress test is carried out.

REFERENCES:
patent: 4458338 (1984-07-01), Giebel et al.
patent: 4608666 (1986-08-01), Uchida
patent: 4751679 (1988-06-01), Dehganpour
patent: 4860261 (1989-08-01), Kreifels et al.
patent: 4870618 (1989-09-01), Iwashita
patent: 4922453 (1990-05-01), Hidaka

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