Static information storage and retrieval – Read/write circuit – For complementary information
Reexamination Certificate
2000-12-29
2002-01-22
Mai, Son L. (Department: 2818)
Static information storage and retrieval
Read/write circuit
For complementary information
C365S207000, C365S063000
Reexamination Certificate
active
06341088
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and, mainly, to a technique which is effective when utilized in a dynamic RAM (Random Access Memory) including switch MOSFETS between a sense amplifier and bit lines.
The dynamic RAM, which is intended to raise the speed of the sense amplifier by turning OFF the selected side of a shared select MOSFET temporarily to lighten the load on the sense amplifier, has been disclosed in Japanese Patent Laid-Opens Nos. 64-73596, 5-62463 and 8-106781. In Japanese Patent Laid-Open No. 4-167293, on the other hand, there is disclosed a dynamic RAM. In this dynamic RAM, switch MOSFETs, which are interposed between the input/output nodes of the sense amplifier and complementary bit lines, are first set to the unselect level at the time of starting the amplification of the sense amplifier, so that the sense amplifier and the complementary bit lines are isolated to start the amplifying operations. After a column selection, the gate voltage of the switch MOSFETs is set to an intermediate potential to perform the operations in parallel to output one of the sense amplifier amplification signals to the IO lines and to restore the other amplification signal in the bit lines. After this, the gate voltage of the switch MOSFETs is returned to the select level so that the one amplification signal is re-stored through the bit lines in the memory cells.
Here, the terminlogy “MOS(Metal Oxide Semiconductor)FET” includes a “MIS (Metal Insulated Semiconductor)FET according to general recognition, and widely refers to a field effect transistor.
SUMMARY OF THE INVENTION
As in the dynamic RAM disclosed in Japanese Patent Laid-Opens Nos. 64-73596, 5-62463 and 8-106781, before the amplification start of the sense amplifier, the shared select MOSFETs are turned OFF to isolate the complementary bit lines and the sense nodes of the sense amplifier. The sense nodes, even if at a full amplification level state, are lowered at their level, when the shared select MOSFETs are returned again to the ON state. By the charge share between the read charge from the memory cells held in a relatively high parasitic capacity of the bit lines and the charge in the sense nodes, the potential of the sense nodes drops so that the signal amplitude is temporarily reduced, as clarified by our investigations. Alternatively, even when the sense nodes are connected with the data output lines by the column selecting operation, the signal amplitude of the sense nodes is also temporarily reduced, as clarified by our investigations, by the charge share between the precharge charge held in the parasitic capacity of the data output lines and the charge in the sense nodes. As a result, in the column selecting operation, the column selecting operation has to take a relatively long time for transmitting the signal of the sense nodes to the data input/output lines, and this long time causes an obstruction to the high speed, as also clarified by our investigations.
In the Japanese Patent Laid-Open No. 4-167293, the gates of the switch MOSFETs are set to the intermediate potential to cause the sense amplifier to effect outputting at the low level to the I/O lines. In parallel with this, the re-storage (or reloading) of the data is effected in the bit lines on the high level side. As well known in the art, however, the memory cells store the binary information. Even if the re-storage of the data on the high level side is exclusively accelerated, as described above, the effect in view of the overall memory access is questionable, as clarified by our investigations, considering that the data re-storage on the low level side is not performed before the switch MOSFETs are returned to the ON state. On the other hand, that effect involves a problem in that the timing control at the level is complicated, as clarified by our investigations, considering that the gate voltage to be fed to the gate of one switch MOSFET is changed between the unselect level—the select level—the intermediate level—the unselect level within a short time period from just before the start of the sense operation to the restoring operation of the bit lines, so that the provision of the switch MOSFETs makes no sense if the transfer from the select level to the intermediate level is not made before the sense output grows sufficient, and the elements have a process dispersion. It has been further clarified by our investigations that the change from the intermediate level to the unselect level raises an obstruction to the high speed of the re-storage operations.
An object of the invention is to provide a semiconductor memory device which has realized a stable amplifying operation and a high speed in a sense amplifier with a simple construction. The foregoing and other objects and novel features of the invention will become apparent from the description to be made with reference to the accompanying drawings.
Representative aspects of the invention to be disclosed herein will be briefly summarized in the following. Specifically, switch MOSFETs are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines. After signal voltages have been read out by the selecting operations of said word lines , from a plurality of selected dynamic memory cells, to the plurality of pairs of complementary bit lines in accordance with their individual storage informations, the switch control signal of said switch MOSFETs is changed from a select level to the intermediate potential having: (a) an OFF state or a relatively high ON resistance for the signal voltage read out to said complementary bit lines; (b) an ON state with a relatively low ON resistance for a potential at which the sense nodes are set to one level by the amplifying operation of the sense amplifier; and (c) an OFF state at a potential of the other level. The sense amplifier is fed with an operating voltage to start the amplifying operation in response to the change in said switch control signal; an amplification signal generated by said amplifying operation is transmitted through the column select circuit to said input/output lines in response to the column select signal; and said switch control signal is returned to the select level in response to the selecting operation of said column select circuit.
With the construction thus far described, in the amplifying operation of the sense amplifier, one of the sense nodes is connected with the bit line so that a high signal charge can be established by the parasitic capacity on the bit lines. In the column selecting operation, therefore, a high read signal can be outputted to the data input/output lines thereby to effect the high speed of the sense output operation.
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Nagashima Osamu
Sakamoto Tatsuya
Takemura Riichiro
Antonelli Terry Stout & Kraus LLP
Auduong Gene N.
Mai Son L.
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