Dynamic random access memory having stacked type capacitor and m

Details Dynamic random access memory having stacked type capacitor and m Dynamic random access memory having stacked type capacitor and m

1993-06-30

1995-01-10

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Capacitors

257301, 257302, 257303, 257306, 257307, 257296, H01L 2968, H01L 2710

Patent

active

053813650

ABSTRACT:
The DRAM according to the present invention comprises so-called cylindrical stacked type capacitors. Each of the cylindrical stacked type capacitors comprises a base portion extending flat on an insulation layer and a surface of a substrate, and a cylindrical portion extending vertically and upwardly from the base portion. Then, the cylindrical portion vertically and upwardly protrudes from an outermost peripheral position of the base portion. As a result, an area where electrodes of the capacitor and capacitance of the capacitor can be increased. Furthermore, with a bit line located below an electrode layer of the capacitor, adjacent capacitors above the bit line can be isolated. Accordingly, it is possible to prevent the bit line contact from defining an isolation distance between the capacitors. Furthermore, an isolating layer patterned by etching is used as an isolating region between the capacitors and a lower electrode of the capacitor is formed along a surface of the isolating layer to form an isolation region between the adjacent capacitors. In addition, the lower electrode of the cylindrical stacked type capacitor is integrally formed by using a step formed in the insulation layer. As a result, the manufacturing step is simplified.

REFERENCES:
patent: 5047817 (1991-09-01), Wakamiya et al.
patent: 5101251 (1992-03-01), Wakamiya et al.
patent: 5218219 (1993-06-01), Ajika et al.
Ema et al., "3-Dimensional Stacked Capacitor Cell For 16M DRAMs" 1988 IEEE Yamada et al., Spread Source/Drain (SSD) MOSFET Usig Selective Silicon Growth for 64Mbit DRAMs, IEDM 89, pp. 35-38.
Wakamiya et al., "Novel Stacked Capacitor Cell for 64Mb DRAM", LSI R&D Laboratory, Itami 664 Japan, pp. 69-70.
Kawamoto et al., "A 1.28 .mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64Mb DRAMs", 1990 Symposium on VLSI Technology, pp. 13-14.
Inoue et al., "A New Stacked Capacitor Cell with Thin Box Structured Storage Node", Extended Abstracts of the 21st Conference on Solid State Devices and Materials, 1989, pp. 141-144.

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