Static information storage and retrieval – Read/write circuit – For complementary information
Patent
1996-10-23
1997-09-30
Nelms, David C.
Static information storage and retrieval
Read/write circuit
For complementary information
36523003, 3652335, 36518909, 365193, G11C 700
Patent
active
056732260
ABSTRACT:
The present invention relates to a high-speed data transmission system for efficiently transmitting large amounts of data within short periods of time. A DRAM comprises at least a memory cell, sense amplifiers, a /RAS signal input, a word line (WL) boost signal generator, a sense amplifier control signal-generator, and a sense amplifier drive signal-generator, wherein the memory cell is constituted by a plurality of banks, the sense amplifiers are provided in a corresponding plurality of numbers, the sense amplifier control signal-generator are provided in a plurality of numbers to correspond to the plurality of banks, and provision is made of external sense amplifier activating signal terminals which are connected to the sense amplifier control signal-generator in order to activate the sense amplifiers independently of the /RAS signal.
REFERENCES:
patent: 4984210 (1991-01-01), Kumanoya et al.
patent: 5132932 (1992-07-01), Tobita
patent: 5251180 (1993-10-01), Ohshima
patent: 5267203 (1993-11-01), Hwang et al.
patent: 5319253 (1994-06-01), You
Fujii Yasuhiro
Yumitori Fuminori
Fujitsu Limited
Nelms David C.
Tran Andrew Q.
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