Static information storage and retrieval – Read/write circuit – Signals
Patent
1992-01-31
1994-05-24
Dixon, Joseph L.
Static information storage and retrieval
Read/write circuit
Signals
365222, 365226, 365228, 365233, G11C 700, G11C 800
Patent
active
053155505
ABSTRACT:
This dynamic random access memory having a plurality of rated voltages as an operation supply voltage operates accurately with a sufficient operating margin for each rated voltage. The dynamic random access memory comprises a circuit (200; 120, 130) for generating a signal for defining operation speed/timing of a sense amplifier (50) depending on the operation supply voltage, and a circuit (210) for driving the sense amplifier in response to an output of a defining signal generating circuit. The sense amplifier driving circuit comprises a first gate (G1) for transmitting a sense amplifier activating signal as it is in response to the defining signal, a second gate (G2) for passing therethrough a sense amplifier activating signal passed through a delay circuit (100) in response to the defining signal, and transistors (25, 25'; 25) for driving the sense amplifier in response to outputs of the first and second gates. One of the first and second gates is activated by the defining signal. An operation speed/timing instructing signal is applied externally or from a supply voltage detecting circuit (300). In the case that rated values are varied depending on an operation mode, there are provided a circuit (130) for detecting the operation mode in response to activating timings of a row address strobe signal, a column address strobe signal and a write signal, and a circuit (120) for generating a defining signal in response to an output of this operation mode detecting circuit and the operation speed/timing instructing signal.
REFERENCES:
patent: 4061954 (1977-12-01), Proebsting et al.
patent: 4616346 (1986-10-01), Nakaizumi et al.
patent: 4631707 (1986-12-01), Watanabe
patent: 4672586 (1987-06-01), Shimohigashi et al.
patent: 4686386 (1987-08-01), Tadao
patent: 4800533 (1989-01-01), Arakawa
patent: 4811290 (1989-03-01), Watanabe
patent: 4831595 (1989-05-01), Bone
patent: 4881205 (1989-11-01), Aihara
patent: 4939695 (1990-07-01), Isobe et al.
patent: 4943960 (1990-07-01), Komatsu et al.
patent: 5031150 (1991-07-01), Ohsawa
Nikkei Electronics Publication, Jan. 8, 1979, pp. 110-133. (with translation).
Nikkei Electronics Publication, No. 451, Jul. 11, 1988, pp. 181-193.
Dixon Joseph L.
Mitsubishi Denki & Kabushiki Kaisha
Whitfield Michael A.
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