Dynamic random access memory having row decoder with level trans

Details Dynamic random access memory having row decoder with level trans Dynamic random access memory having row decoder with level trans

1995-05-05

1997-12-09

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518909, 36523006, 36523003, 326106, 326108, G11C 702

Patent

active

056967217

ABSTRACT:
A circuit is designed with a decoder circuit (10), responsive to a first input signal (81) having a first voltage range, for producing a first output signal. An output circuit (11), responsive to the first output signal, produces a second output signal (26) having a second voltage range. The second voltage range includes a voltage less than a least voltage of the first voltage range and a voltage greater than a greatest voltage of the first voltage range.

REFERENCES:
patent: 4628486 (1986-12-01), Sakui
patent: 5297104 (1994-03-01), Nakashima
patent: 5363338 (1994-11-01), Oh
patent: 5410508 (1995-04-01), McLaury

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