Dynamic random access memory having no capacitor and method for

Static information storage and retrieval – Systems using particular element – Capacitors

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G11C 700

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active

057989656

ABSTRACT:
A capacitor-less dynamic random access memory (DRAM) having a unit cell includes a first transistor receiving data through a source electrode connected to a bit line according to a signal level applied to a gate electrode, and a second transistor storing charges corresponding to data input to the first transistor and outputting a reference voltage to the bit line according to the level of the charges. This improves the reliability and integration of the device.

REFERENCES:
patent: 3771148 (1973-11-01), Aneshamsley
patent: 4716548 (1987-12-01), Mochizuki
patent: 5122986 (1992-06-01), Lim
patent: 5282162 (1994-01-01), Ochii
patent: 5448513 (1995-09-01), Hu et al.
"A Capacitorless DRAM Cell on SOI Substrate", Wann et al., IEDM 93, pp. 635-638, 1993.

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