Static information storage and retrieval – Read/write circuit – Complementing/balancing
Reexamination Certificate
2000-08-10
2002-01-08
Lane, Jack A. (Department: 2185)
Static information storage and retrieval
Read/write circuit
Complementing/balancing
C365S203000, C365S205000, C365S207000, C365S233500
Reexamination Certificate
active
06337821
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) which has synchronous data transfer means.
2. Description of the Related Art
Two of the important points in designing a large-scale integrated circuit (LSI) are an increase in the operating speed at which the LSI operates, and a reduction in the power the LSI consumes. The hither the integration density of the LSI, the greater the capacitance and resistance of the data lines which connects the circuit blocks of the LSI. When the LSI data lines have a great capacitance and a high resistance, the performance of the LSI decreases. To set the LSI performance at a sufficiently great value despite of the great capacitance and high resistance of the data lines, a data transfer control system is used. This system comprises a differential amplifier connected between an input data line and an output data line of the LSI, and an equalizing circuit connected to the output terminal of the differential amplifier. First, the equalizing circuit resets the data on the output data line. Then, the data is transferred from the input data line to the output data line.
The data transfer control system described above makes it possible to transfer data at high speed, even if the data lines, in particular the output data lines, have a large capacitance or a high resistance. The reason why will be explained briefly. If new data is transferred from the input data line from the output data line, with the old data remaining on the data output line, the differential amplifier needs to drive the output data line, thereby to invert the old data and form new data. In order to perform this task, the amplifier must have a great drivability. Hence, if the output data line has a great capacitance or a high resistance, data cannot be transferred at high speed. In the data transfer control system, data can be transferred at high speed even if the differential amplifier has no great drivability, since the equalizing circuit resets the output data line prior to the data transfer.
Even if the data transfer control system is used, however, the transfer of the new data is delayed if it takes a long time to equalize the output data line. The delay in transferring the new data is a bar to high-speed operation and makes a great problem to a recently developed large-chip LSI, in particular a DRAM comprising data lines which are thin and long and, hence, have a great capacitance or a high resistance. To be more specific, the operating speed of the I/O data buffer incorporated in a DRAM, for transferring data to, and receiving data from, external devices, is very important.
As has been described, in the great problem with the I/O data buffer used in the conventional large-scale DRAM, it takes a long time to equalize the data lines, inevitably reducing the speed of data transfer.
SUMMARY OF THE INVENTION
The object of the invention is to provide a DRAM having means which can transfer data at a sufficiently high speed.
To accomplish this object, a DRAM according to the present invention comprises:
a memory-cell array having a plurality of parallel bit lines, a plurality of parallel word lines intersecting with the bit lines, and a plurality of dynamic memory cells located at intersections of the bit lines and the word lines;
a sense amplifier for supplying data to and receiving data from any selected one of the memory cells;
an address buffer having an output terminal and designed to store a row address and a column address externally supplied;
a column decoder located near the memory-cell array, for selecting one of the bit lines in accordance with the column address output from the address buffer;
a row decoder located near the memory-cell array, for selecting one of the word lines in accordance with the row address output from the address buffer;
a transfer gate selectively controlled by said column decoder;
first data lines connected to the bit lines by the transfer gate;
a data input/output buffer connected to the first data lines;
second data lines connected to the first data lines by the data input/output buffer;
an address-transition detecting circuit connected to the output terminal of the address buffer, for detecting transition of the row and column address signals output from the address buffer and for outputting a signal upon detecting the transition of the row and column address signals;
an equalizing circuit connected to the second data lines, for maintaining the second data lines in reset condition during normal operation, and for temporarily releasing the second data lines from the reset condition in response to the signal output from the address-transition detecting circuit; and
a data-latching circuit connected to the second data lines, for latching data transferred to the second data lines, in response to the signal output from the address-transition detecting circuit.
In the DRAM of the invention, the second data lines remain in the reset (equalized) condition until address transition occurs at the output of the address buffer. When address transition occurs, the second data lines are released from the reset condition, whereby data is transferred from the first data lines to the second data lines almost at the same time the address transition takes place. The data transferred to the second data lines is latched by the data-latching circuit. The second data lines are therefore made ready for receiving the data which will be transferred from the first data lines when address transition occurs. No time is therefore required to equalize either data lines, unlike in the conventional data transfer control system. Hence, data can be transferred at high speed in the DRAM according to the present invention.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
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ISSCC 84/Thursday, Feb. 23, 1984/Continental Ballrooms 5-9/3:45 P.M.; Session XV: Static RAMs; Osamu Minato et al; 1984 IEEE International Solid-State Circuits Conference; pp. 222-223.
Tsuchida Kenji
Watanabe Yohji
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