Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2004-12-21
2008-09-16
Torres, Joseph D (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07426675
ABSTRACT:
A dynamic random access memory circuit including a memory plane composed of an array of memory cells arranged in lines and columns, and a line decoder, each line of the memory plane corresponding to a page of words. Two buffer registers are coupled with the memory plane for reading words in a page of the memory and for writing new words to a page of the memory, and the registers are used alternatively to access this memory plane. The buffer registers are dual-port memories and, moreover, the memory has an error correcting circuit allowing read-modify-write cycles applied to a group of n words within the same page. Whereby the reliability of the memory circuit is substantially increased and, moreover, an alternative solution to burn-in can even be offered. The invention also provides a method for controlling a dynamic memory having an error correcting code mechanism.
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Satagaj Thomas J.
Seed IP Law Group PLLC
STMicroelectronics S.A.
Torres Joseph D
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