Dynamic random access memory having an improved operational stab

Details Dynamic random access memory having an improved operational stab Dynamic random access memory having an improved operational stab

1992-11-05

1994-07-05

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Data refresh

36518901, G11C 800

Patent

active

053273877

ABSTRACT:
A dynamic random access memory comprises a CBR refresh detection unit for detecting a commencement of a CBR refreshing cycle and a control signal generation unit for deactivating data output during the CBR cycle, both of the CBR refresh detection unit and the control signal generation unit being supplied with a /RAS signal and a /CAS signal simultaneously, wherein the dynamic random access memory further comprises a CBR refresh control unit supplied with an output of the CBR refresh detection unit and further with an output of the control signal generation unit for producing a control signal during the CBR refreshing cycle such that the control signal is produced in response to the leading edge of the /RAS signal and terminated in response to the trailing edge of the /CAS signal. Thereby, an output buffer circuit is controlled in response to the output of the control signal generation unit and the control signal of the CBR refresh control unit to set the output buffer circuit in the high impedance state during the CBR refreshing cycle.

REFERENCES:
patent: 4747082 (1988-05-01), Minato et al.
patent: 4827453 (1989-05-01), Sawada et al.
patent: 4984208 (1991-01-01), Sawada et al.

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