Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1991-09-19
1993-09-14
James, Andrew J.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257638, 257644, 257758, H01L 2968
Patent
active
052452050
ABSTRACT:
A dynamic random access memory comprises a memory cell region and a sense amplifier region defined on a substrate, a plurality of memory cell capacitors provided on the memory cell region in correspondence to memory cell transistors, a first insulation layer provided on the semiconductor substrate to cover both the memory cell region and the sense amplifier region, a first conductor pattern provided on the first insulation layer, an intermediate connection pattern provided on the first insulation layer in correspondence to the sense amplifier region, a spin-on-glass layer provided on the first insulation layer to extend over both the memory cell region and the sense amplifier region, and a projection part provided on the substrate of the sense amplifier region in correspondence to the intermediate connection pattern under the first insulation layer for lifting the level of the surface of the first insulation layer such that the intermediate interconnection pattern is exposed above the upper major surface of the spin-on-glass layer. The projection part includes a conductor piece formed from a same conductor material that forms an opposing electrode of the memory cell capacitor. Further, a second insulation layer is provided on the spin on glass layer to bury the first conductor pattern and the intermediate conductor pattern, and a contact hole is provided on the second insulation layer to expose the intermediate conductor pattern. The intermediate conductor pattern is connected electrically to a second conductor pattern provided on the second insulation layer via the contact hole.
REFERENCES:
patent: 4775550 (1988-10-01), Chu et al.
patent: 4959704 (1990-09-01), Isomura et al.
patent: 5068711 (1991-11-01), Mise
patent: 5155064 (1992-10-01), Mise
"Planarization Process Using Spin-on-Glass", Ting et al, IEEE 4th VLSI Multilevel Interconnection Conference, Jun. 16, 1987, pp. 61-77.
Higasitani Masaaki
Nomura Toshio
Shin Daitei
Bowers Courtney A.
Fujitsu Limited
James Andrew J.
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