Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1989-11-16
1992-07-21
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Data refresh
365226, 365228, 365233, G11C 700, G11C 800
Patent
active
051329328
ABSTRACT:
This dynamic random access memory having a plurality of rated voltages as an operation supply voltage operates accurately with a sufficient operating margin for each rated voltage. The dynamic random access memory comprises a circuit (220; 120, 130) for generating a signal for defining operation speed/timing of a sense amplifier (50) depending on the operation supply voltage, and a circuit (210) for driving the sense amplifier in response to an output of a defining signal generating circuit. The sense amplifier driving circuit comprises a first gate (G1) for transmitting a sense amplifier activating signal as it is in response to the defining signal, a second gate (G2) for passing therethrough a sense amplifier activating signal passed through a delay circuit (100) in response to the defining signal, and transistors (25, 25'; 25) for driving the sense amplifier in response to outputs of the first and second gates. One of the first and second gates is activated by the defining signal. An operation speed/timing instructing signal is applied externally or from a supply voltage detecting circuit (300). In the case that rated values are varied depending on an operation mode, there are provided a circuit (130) for detecting the operation mode in response to activating timings of a row address strobe signal, a column address strobe signal and a write signal, and a circuit (120) for generating a defining signal in response to an output of this operation mode detecting circuit and the operation speed/timing instructing signal.
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Nikkei Electronics, Jan. 8, 1979, pp. 110-133 (English Translation).
Nikkei Electronics No. 451, Jul. 11, 1988, pp. 151-193.
Hecker Stuart N.
Mitsubishi Denki & Kabushiki Kaisha
Whitefield Michael A.
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