Static information storage and retrieval – Read/write circuit – Differential sensing
Patent
1987-03-27
1989-02-07
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Differential sensing
365189, G11C 702
Patent
active
048036641
ABSTRACT:
Integration of a dynamic random access memory having a very high integration is further improved according to the invention. A memory structure is disclosed wherein a three transistor type memory cell is used instead of a conventional lT-lC memory cell, and data read and write terminals are connected to a pair of data lines in such a manner that the electrical characteristics of the pair of data lines are balanced. A three transistor type memory cell is realized which is capable of operating at high speed and with high reliability.
REFERENCES:
patent: 4491858 (1985-01-01), Kawamoto
J. A. Karp et al., "A 4096-Bit Dynamic MOS RAM", Digest of Technical Papers, pp. 10-11, 1972, IEEE International Solid-State Circuits Conference.
K. Shimohigashi et al., "Design of a 3-Transistor, 2.5 Line Per-Bit Dynamic MOS RAM", Institute of Electronics and Communication Engineers of Japan, Jun. 1975, vol. 58-C, No. 6, pp. 327-334.
Hitachi , Ltd.
Popek Joseph A.
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