Dynamic random access memory fabricated with SOI substrate

Details Dynamic random access memory fabricated with SOI substrate Dynamic random access memory fabricated with SOI substrate

1991-12-12

2000-06-06

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257 71, 257350, H01L 2968, H01L 2978, H01L 2992

Patent

active

060722088

ABSTRACT:
In a dynamic random access memory (DRAM), a step produced by forming a stacked capacitor can be prevented from being produced and increased, thereby facilitating the patterning of an upper layer (wiring, etc.). Further, the pattern layout can be made with freedom and the DRAM itself can be highly integrated. This dynamic random access memory is constructed such that stacked capacitors (C.sub.1), (C.sub.2) composed of accumulation node electrodes (7a), (7b), a dielectric layer (8) and a sub-plate electrode (9) are formed on the under layers of a switching element (Tr1) composed of a word line (4a) and two source-drain regions (5a), (5b) and a switching element (Tr2) composed of a word line (4b) and two source-drain regions (5a), (5c).

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