Dynamic random access memory (DRAM) having variable...

Details Dynamic random access memory (DRAM) having variable... Dynamic random access memory (DRAM) having variable...

1998-05-19

2001-01-02

Cabeca, John W. (Department: 2752)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S105000, C711S002000

Utility Patent

active

06170035

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of EPO Application No. 97830231.3 filed May 20, 1997.
1. Technical Field
The present invention relates to a dynamic random access memory (DRAM) for data processing system. The memory can have a variable configuration depending on user requirements, and a capacity which is expandable through non-interleaved memory modules or through interleaved memory blocks, possibly spread over several expansion supports. It also relates to the corresponding expansion support or Memory Riser with which the interleaved memory blocks are made, possibly spread over several supports.
2. Background of the Invention
It is known that in order to meet the various requirements of use of data processing systems, the latter are provided with a random access work memory, of dynamic type (DRAM), whose capacity can be expanded.
A broad example consists of the PCs in which on a motherboard, on which the microprocessor and a memory control unit are installed, is also installed a plurality of connection slots into each of which can be inserted a memory module, of the type commercially available with the acronyms SIMM (Single In Line Memory Module) and DIMM (Dual In Line Memory Module).
These memory modules are essentially small printed circuit boards which, on an edge connector, bear connection terminals and on which board are mounted as many integrated memory components as are necessary to allow the desired memory parallelism.
These modules have in fact become, from the commercial and technological point of view, a standard and with advances in technology have made available modules with ever-growing capacity, at a factor 2
N
relative to a base capacity.
Thus by installing one or more modules in the various available slots (an operation which with the due precautions can even be carried out by the user) it is possible to provide a memory whose capacity can be expanded, as a function of the various user requirements, without burdening the basic product with the cost of a memory having the maximum capacity allowed by the system.
In more advanced systems, memory modules of a certain type can also be substituted by others having a greater capacity, double or quadruple that originally installed.
Thus the connection interface, at slot level, has been defined to allow this possibility and contains a number of address terminals which is suitable for the maximum envisagable (even in view of further technological developments) capacity of the modules.
The interface also provides a suitable number of identification terminals for the transfer, from the module to the system, of signals which make it possible to recognize the type of module and its capacity and hence to configure, by means of configuration logic of the memory control unit, the working memory, in such a way as to address the whole of the available memory space and select in rotation, through read and/or write operations, one of the modules which make up the memory.
The SIMM or DIMM modules (the latter differ from the former through their greater memory capacity, obtained by installing components on both faces of a printed circuit support) therefore make up the memory units installable in the system.
In high-performance data processing systems, generally consisting of a plurality of processors, varying in number depending on requirements, which have access to a shared working memory, it is not sufficient to employ a working memory of large capacity: it is also necessary for several read and/or write operations to be carried out in the working memory with at least partial time overlap, so as to increase the memory throughput.
This is achieved by constructing the memory as a plurality of banks or blocks which can be controlled and addressed independently and amongst which the memory space is divided up according to well known concepts of “interleaving”.
A memory bank or block is therefore defined as the minimum memory unit which can be interleaved.
Configuration logic, which depending on the memory address identifies the block to be used for the read/write operation, is not sufficient to allow memory interleaving: control logic which supplies the necessary timed commands and a latch register which retains the memory address, intended for the block, for the whole of the required time, must also be provided for each block.
Two partitioning approaches are possible in order to produce a memory architecture with interleaved blocks: according to a first approach a motherboard which contains the memory control unit, interfaced with a system bus, also contains all of the control and timing logic and the registers required to drive a maximum number, envisaged by design, of memory blocks.
The memory blocks can consist of one or more memory modules of standard type, for example SIMM or DIMM, mounted on the motherboard via connectors.
With this approach the basic structure of the system is burdened by significant costs for the logic required to manage the maximum memory configuration even when the configuration actually required by the user is smaller on account of memory capacity and level of interleaving required.
With a second approach the various blocks consist of printed circuit daughterboards on which are mounted, in addition to the memory components (possibly varying in number in order to produce various capacities) also the necessary management and timing logic for the block as a component of an interleaved memory structure.
The daughterboards are then each inserted, in varying number depending on the requirements, into various slots of the motherboard.
Upon the control unit on the motherboard devolves the sole task, by means of the memory configuration logic and depending on the memory address, of selecting, from among the various blocks present in memory, that upon which the read/write operation devolves.
With this approach the basic structure of the system is not burdened by the costs of the logic necessary to manage the maximum configuration, but, even when an interleaved memory structure is not required, it is still necessary to employ a memory block, and it is not possible to use instead a standard memory module of SIMM or DIMM type which is more readily obtainable on the market and less expensive.
A further limitation of this approach is that the level of interleaving is closely dependent on the number of blocks installed and hence, to some extent, also on the capacity installed.
A problem common to expandable DRAM memories, be they structured as interleaved blocks or as simple modules, therefore consists in the fact that many signals, and in particular the address signals, have to be sent to a widely varying number of loads.
It is therefore necessary to provide, in order to prevent degradation of the signal edges and erroneous recognitions thereof, in particular if. the memory operation is timed by clock signals of high frequency of the order of 100-150 MHz, as is now current practice, drive buffers, according to a tree structure if arranged at several levels.
These buffers, although on the one hand preventing the degradation of the signal edges, on the other hand introduce propagation delays which have to be taken into account in the mutual timing of the signals and however allocated, on the motherboard or in the memory blocks, they indiscriminately increase the memory access time irrespective of the memory configuration actually present.
Thus, the worst timing case should be considered.
SUMMARY OF THE INVENTION
These limitations and drawbacks are eliminated from the dynamic random access memory which is the subject of the present invention which provides for the use of memory modules of DIMM type inserted directly into slots in a motherboard, varying in number, to obtain a memory configuration with varying capacity depending on the number and type of modules installed, and also the alternative or combined use of printed circuit expansion supports which, these too, are inserted into the same slots in the motherboard, envisaged for the DIMM modules, and which in turn are provide

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