Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-06-20
2002-09-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S052000, C365S191000, C365S230080
Reexamination Certificate
active
06452828
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 2000-61256, filed on Oct. 18, 2000, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit memories, and more particularly to a structure of word line low voltage supply lines in dynamic random access memory (DRAM) devices capable of minimizing noise caused by loading differences of word line low voltage supply lines.
2. Backword line low of the Invention
A dynamic random access memory (DRAM) device as a volatile memory device includes memory cells, each consisting of a cell transistor or a switch transistor and a capacitor. The term ‘cell transistor’ as used here will include switch transistors. In general, the cell transistor of the memory cell is a N-channel metal-oxide semiconductor (NMOS) transistor. A retention time of data held in the memory cell is affected by a leakage current running from a source to a drain, or through a channel, in the cell transistor. The leakage current may be, generated from word line low noise arising when the word line is not sufficiently discharged to the word line low potential, even after a read/write operation is over.
FIG. 1
is a block diagram showing a layout arrangement of word line low supply lines in the conventional DRAM device.
Referring to
FIG. 1
, the DRAM device includes a plurality of sub arrays
10
arranged in a matrix with rows and columns, and each of the sub arrays
10
is formed of a plurality of memory cells MC coupled to word lines WL, and bit line pairs BL and /BL. Sense amplification regions
20
are disposed between the sub arrays
10
arranged along the row direction. Each of the sense amplification regions
20
includes a plurality of sense amplifiers which are connected to the bit line pairs BL and /BL extended along rows. As known in the art, the sense amplifiers in the sense amplification regions
20
are shared with the adjacent sub arrays
10
.
Continuing to refer to
FIG. 1
, sub-word line drive regions
30
are disposed between the sub arrays
10
along the column direction. Each of the sub-word line drive regions
30
includes a plurality of word line drivers WLD. A portion of the word lines WL in each of the sub arrays
10
is selected by the word line drivers WLD of sub-word line drive regions
30
disposed on one side of the sub arrays
10
, and the rest of the word lines are selected by the word line drivers WLD of sub-word line drive regions
30
disposed on the other side. Conjunction regions
40
are disposed between the sub-word line drive regions
30
along the row direction.
As well known to those skilled in the art, the foregoing structure is called a “bank”. As shown in
FIG. 1
, the bank includes word line drive word line low supply lines VssW, array power supply lines VccA, and array word line low supply lines VssA disposed therein.
In specific, the VccA and the VssA are disposed over the sense amplifying regions
20
and the conjunction regions
40
arranged in the column direction. The VssW are disposed over the sub-word line drive regions
30
and the conjunction regions
40
arranged in the row direction, and extended along the column direction from one side of the bank. The word line drivers WLD of the sub-word line drive regions
30
are coupled to the VssW.
A word line is selected, and a read/write operation is performed. After the operation is terminated, the potential of the selected word line is discharged from a predetermined word line voltage to a word line low potential. Here, an outline of a discharging path is the selected word line, the word line driver, the VssW, and a word line low potential pad (not shown).
One end of VssW extending along the row direction retains a floating state, and the other end thereof is coupled to the word line low potential pad. Briefly, elements affecting the loading performance of the VssW are figured out in various forms at the sub-word line drive regions
30
arranged along the row direction. Thus, the selected word lines WL adjacent to the VSSW coupled to the word line low potential pad are sufficiently discharged to the word line low potential, while the other selected word lines WL far from the VSSW relative to the near-positioned word lines are not sufficiently discharged. The cell transistor connected to the word line that is insufficiently discharged to the word line low potential is slightly turned on, and thereby electric charges held in the capacitor are leaked. Subsequently, the word line low noise may reduce the data retention time.
SUMMARY OF THE INVENTION
In order to attain the above objects, an embodiment of the present invention, there is provides a dynamic random access memory (DRAM) device having a plurality of cell arrays each of which is formed of memory cells coupled to word lines and bit lines in a matrix, the device including: regions of sense amplifiers disposed between the cell arrays arranged along the row direction; regions of word line drivers disposed between the cell arrays arranged along the column direction; conjunction regions disposed at positions adjacent to the regions of the sense amplifiers and word line drivers; and a plurality of word line low voltage supply lines disposed on the conjunction regions. The word line low voltage supply lines are electrically interconnected with each other at least on the conjunction regions. The word line low voltage supply lines are connected to a word line low voltage source through a pad.
According to the constitution of DRAM device of the present invention, loading of word line low voltage supply lines for driving word lines are equally distributed over all bank regions regardless of a disposition of cell arrays.
The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.
REFERENCES:
patent: 6180448 (2001-01-01), Lee
Choi Jong-Hyun
Kang Sang-Seok
Lee Jong-Eon
Auduong Gene N.
Marger Johson & McCollom, P.C.
Nelms David
Samsung Electronics Co,. Ltd.
LandOfFree
Dynamic random access memory (DRAM) having a structure for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic random access memory (DRAM) having a structure for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic random access memory (DRAM) having a structure for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2858864