Dynamic random access memory (DRAM) cells with minimum active ce

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257301, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

060085134

ABSTRACT:
A method for making DRAM cells with minimum active device areas (cell areas) using novel sidewall-spacer bit lines is achieved. A trench is etched in an insulating layer aligned over the device areas and orthogonal to the gate electrodes, and extending over the first and second source/drain areas. A conducting layer is deposited and etched back to form sidewall-spacer bit lines. A planar second insulating layer is formed in which bit line contact openings are etched between the sidewall-spacer bit lines to the first source/drain areas. The contact openings are filled with a third conducting layer to form the bit line contacts. A third insulating layer is deposited and capacitor node contact openings are etched between the sidewall-spacer bit lines and to the second source/drain areas. An insulating layer is deposited and etched back to insulate the sidewall-spacer bit lines in the node contact openings and a fourth con-ducting layer is deposited and etched back to form the node contacts. By this self-aligned method, the minimum unit cell area (device area) can be reduced to about 6F.sup.2, where F is the minimum feature size for the current technology. Any one of the current stacked capacitor structures, such as crown, fin-shaped, and the Like, can now be built on the node contacts to provide memory cells with increased packing density.

REFERENCES:
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patent: 5281837 (1994-01-01), Kohyama
patent: 5409855 (1995-04-01), Jun
patent: 5482886 (1996-01-01), Park et al.
patent: 5622883 (1997-04-01), Kim

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