Dynamic random access memory (DRAM) cell with folded bitline...

Details Dynamic random access memory (DRAM) cell with folded bitline... Dynamic random access memory (DRAM) cell with folded bitline...

2002-03-21

2004-04-13

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S328000

Reexamination Certificate

active

06720602

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a dynamic random access memory (DRAM) cell, and more particularly to a DRAM cell with a folded bitline vertical transistor.
2. Description of the Related Art
Some conventional DRAM memory systems utilize folded bitline sensing. Such conventional folded bitline architectures permit the rejection of common-mode noise components between adjacent cells in the array, and across the array. Array cells with an area >8F
2
(e.g., F is equal to one minimum feature size) typically use an active wordline and a passing wordline (2F+2F=4F pitch) across each cell to obtain folded bit sensing with a single level of wiring for the bitline.
However, there are some problems of the conventional architecture when applied to an open-bitline array cell with area <8F
2
. For example, common-mode array noise rejection of open-bitline sub-8F
2
DRAM cell arrays is reduced relative to the conventional folded 8F
2
DRAM cell.
An additional bitline wiring level may be added to provide a vertical folding (e.g., see Hoernigschmid et al., IEEE Journal of Solid State Circuits, Vol. 35, No. 5, May 2000, page 713), but there is an increased cost and complexity of the additional bitline wiring level (for vertical global folding) in the sub-8F
2
DRAM.
Additionally, the vertical folding as described in Hoernigschmid et al., IEEE Journal of Solid State Circuits, Vol. 35, No. 5, May 2000, page 713), will only provide common mode rejection of noise components which are introduced on the spatial scale of the vertical folding bitline interchange interval over the array. Noise components which are introduced on a spatial scale of less than the bitline interchange interval in the array will not be rejected by the sense amplifiers, and will degrade product operation margins.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the conventional architecture, it is an object of the present invention to provide a structure (and method for producing the structure) for providing a small (e.g. sub-6F
2
) DRAM cell with a folded bitline vertical transistor which overcomes the above-mentioned problems of the conventional architecture.
Another object is to provide a DRAM cell with a half-pitch wordline and vertical device array access transistor.
In a first aspect of the present invention, a method (and semiconductor device formed thereby) of forming a semiconductor device, includes forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.
With the unique and unobvious aspects and features of the invention, a half-pitch wordline is provided which achieves locally-folded sensing, and common-mode rejection of noise components introduced on the scale of adjacent cells, and on the scale of the array.
Additionally, a half-pitch wordline eliminates the need for an additional bitline wiring level.
Further, with the invention, a vertical array cell access transistor channel length may be scaled independently of the lithographic ground rule.


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