Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2005-09-13
2005-09-13
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S051000, C365S072000, C365S063000, C365S206000, C365S190000, C365S230030, C365S230060
Reexamination Certificate
active
06944080
ABSTRACT:
A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring using the common electrodes.
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Kajigaya Kazuhiko
Kimura Katsutaka
Nakamura Yoshitaka
Sekiguchi Tomonori
Takahashi Tsugio
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Hitachi , Ltd.
Reed Smith LLP
Tran Andrew Q.
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