Dynamic random access memory device with self-refresh cycle time

Details Dynamic random access memory device with self-refresh cycle time Dynamic random access memory device with self-refresh cycle time

1994-02-10

1995-05-23

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

365201, 36518901, 365239, 36518908, G11C 11406, G11C 11403

Patent

active

054187540

ABSTRACT:
A dynamic random access memory device enters into a self-refresh mode in response to a CAS-before-RAS sequence, and a controller incorporated in the dynamic random access memory device deactivates a column addressing system and a data output system in the self-refresh mode for decreasing a current consumption, wherein the controller is responsive to an external test control signal for temporally activating the column addressing system and the data output system, and a self-refresh cycle time is directly measured at a data output pin.

REFERENCES:
patent: 5146430 (1992-09-01), Torimaru et al.
patent: 5315557 (1994-05-01), Kim et al.
patent: 5317709 (1994-05-01), Sugimoto

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