Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1993-07-23
1994-08-09
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Data refresh
365201, 365228, G11C 700, G11C 1140
Patent
active
053372824
ABSTRACT:
A dynamic random access memory device periodically refreshes data bits stored in the memory cells, and a refreshing system is incorporated in the dynamic random access memory device for incrementing a refresh address, wherein the refreshing system comprises an oscillator powered with a step-down voltage in the refreshment and with an external power voltage through a testing operation in a diagnostic mode, a clock generating unit for producing a clock signal defining an interval of each refreshing sequence, and a refresh address counter for producing an internal address signal indicative of the refresh address so that the frequency of a pulse signal produced by the oscillator is regulable without any influence of non-regulated step-down voltage.
REFERENCES:
patent: 4688196 (1987-08-01), Inagaki et al.
patent: 4807196 (1989-02-01), Mizukami
patent: 5144585 (1992-09-01), Min et al.
patent: 5153452 (1992-10-01), Iwamura et al.
patent: 5270982 (1993-12-01), Watanabe
Tohru Furuyama et al., "A New On-Chip Voltage Converter for Submicrometer High-Density DRAM's", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 3, Jun. 1987, pp. 437-441.
LaRoche Eugene R.
NEC Corporation
Nguyen Tan
LandOfFree
Dynamic random access memory device with refreshing system power does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic random access memory device with refreshing system power, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic random access memory device with refreshing system power will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-221530