Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1998-10-13
1999-12-14
Nelms, David
Static information storage and retrieval
Read/write circuit
Data refresh
36518902, 365154, G11C 700
Patent
active
060026286
ABSTRACT:
A dynamic random access memory device with reduced refresh duration, and corresponding refresh process includes a plurality of memory cells. All of the memory cells of one and the same column are connected between two column metallizations, and each comprise four insulated-gate field-effect transistors. The four transistors include two storage transistors both possessing the same first quotient of their channel width to their channel length. The four transistors also include two access transistors both possessing the same second quotient of their channel width to their channel length. The ratio of the first quotient to the second quotient is greater than or equal to one. The ratio of the capacitance of a column metallization and the gate/source capacitance of each storage transistor is at least equal to 50. During a specific refresh cycle, several memory cells of one and the same column are selected simultaneously.
REFERENCES:
patent: 4023149 (1977-05-01), Bormann et al.
patent: 5881010 (1999-03-01), Artieri
"New Architecture of Transparent Refresh For RAM", IBM Technical Disclosure Bulletin, vol. 32, No. 12, May 1, 1990, pp. 271-273.
Lam David
Nelms David
STMicroelectronics S.A.
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