Dynamic random access memory device with bit lines partially sha

Details Dynamic random access memory device with bit lines partially sha Dynamic random access memory device with bit lines partially sha

1992-02-25

1993-09-07

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Semiconductive

365 63, 36518901, 365206, G11C 506

Patent

active

052435580

ABSTRACT:
A dynamic random access memory device in the folded bit line configuration comprises first sense amplifier circuits located on one side of sets of bit lines associated with first transfer units, second sense amplifier circuits located on the other side of the sets of bit lines asoicated with second transfer units, and sets of word lines, and each sets of bit lines and each set of word lines respectively consist of first to third bit lines and first to third word lines for providing nine addressable locations, wherein memory cells are provided at six addressable locations selected from the nine addressable locations, and each set of bit lines respectively propagate two data bits read out from two of the six memory cells to the first and second sense amplifier circuits, thereby increasing the number of memory cells in a unit area.

REFERENCES:
patent: 5091887 (1992-02-01), Asakura
patent: 5097441 (1992-03-01), Cho et al.
patent: 5107459 (1992-04-01), Cho et al.
patent: 5155700 (1992-10-01), Min et al.

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