Dynamic random access memory device with a latching mechanism th

Details Dynamic random access memory device with a latching mechanism th Dynamic random access memory device with a latching mechanism th

1998-01-20

1999-12-21

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Data refresh

36523003, 365149, 36518902, G11C 700

Patent

active

060058188

ABSTRACT:
A dynamic access memory (DRAM) device includes a plurality of memory cells for storing data signals. The DRAM device has a row decoding mechanism that allows selected memory cells to be accessed upon receipt of a row address signal during a read operation and a write operation. A latching mechanism is provided and receives and holds onto the data signals from the selected memory cells when activated during the read operation and also isolates itself from the selected memory cells when deactivated during the write operation. An included refresh address generating mechanism generates a plurality of internal row address signals that allows selection of a plurality of memory cells for refreshing the stored data signals. The DRAM device also has a multiplexer mechanism that transmits a plurality of external row address signals to the row decoding mechanism in the write operation. The multiplexer mechanism also transmits internal row address signals from the refresh address generating mechanism during the read operation, thereby causing the row decoding mechanism to apply the internal row address signals to select memory cells and allow their stored data signals to be refreshed. Therefore, DRAM refresh operations can be performed concurrently during read operations.

REFERENCES:
patent: 4185323 (1980-01-01), Johnson et al.
patent: 5146430 (1992-09-01), Torimaru et al.
patent: 5253211 (1993-10-01), Suzuki
patent: 5367493 (1994-11-01), Yamagata
patent: 5835401 (1998-11-01), Green et al.

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