Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1993-04-09
1994-09-20
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Data refresh
365201, G11C 700
Patent
active
053495624
ABSTRACT:
A dynamic random access memory (DRAM) having an improved refresh control circuit (20) is disclosed. A self-refresh control circuit (15) includes an oscillating circuit (13) for generating a clock signal (.phi.0) defining a refresh cycle in a normal self-refresh mode, and an oscillating circuit (16) for generating a clock signal (.phi.t) defining a refresh cycle in a test mode. When a high voltage higher than a level of a power supply voltage Vcc is applied to a RAS input terminal (22), a test mode detecting circuit (19) provides a high level signal (CTE), thereby turning on a transmission gate (18). In a self-refresh function verification test, since a refresh counter can generate a refresh address having a refresh cycle shorter than in the normal self-refresh mode, time required for carrying out the test may be shortened.
REFERENCES:
patent: 4716551 (1987-12-01), Inagaki
patent: 4933907 (1990-06-01), Kumanoya et al.
patent: 4935900 (1990-06-01), Ohsawa
patent: 5243576 (1993-09-01), Ishikawa
Digest of Technical Papers of IEEE International Solid-State Circuits Conference, Feb. 15, 1985, pp. 252-253.
LaRoche Eugene R.
Le Vu
Mitsubishi Denki & Kabushiki Kaisha
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