Dynamic random access memory device having one-transistor one-ca

Details Dynamic random access memory device having one-transistor one-ca Dynamic random access memory device having one-transistor one-ca

1994-01-13

1995-07-04

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Capacitors

365203, 36523002, 36523003, 36523008, 365150, G11C 1124

Patent

active

054306728

ABSTRACT:
A dynamic random access memory device has a plurality of one-transistor one-capacitor type memory cells each coupled between a first bit line and a second bit line paired with the first bit line, and parasitic capacitance coupled with the first bit line is approximately equal to a parasitic capacitance coupled with the second bit line so that a large potential difference takes place between the first and second bit lines when the storage capacitor is coupled with the first and second bit lines precharged to an intermediate voltage level.

REFERENCES:
patent: 5272665 (1993-12-01), Uesugi
Mikio Asakura et al., "Cell-Plate Line Connecting Complementary Bitline (C.sup.3) Architecture for Battery Operating DRAMs", VLSI Symposium on Circuit, pp. 59-60.

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