Dynamic random access memory device having an improved timing ar

Details Dynamic random access memory device having an improved timing ar Dynamic random access memory device having an improved timing ar

1987-09-30

1989-04-18

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

365233, 365149, G11C 700

Patent

active

048233226

ABSTRACT:
A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.

REFERENCES:
patent: 4376989 (1983-03-01), Takemae
patent: 4656612 (1987-04-01), Allan
patent: 4739502 (1988-04-01), Nozaki
Chwang et al, "A 70ns High Density 64K CMOS Dynamic RAM", IEEE Jour. of Solid State Circuits, vol. SC-18, No. 5, Oct. 1983, pp. 457-463.

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