Dynamic random access memory device having a self refresh mode

Details Dynamic random access memory device having a self refresh mode Dynamic random access memory device having a self refresh mode

1993-04-12

1994-06-14

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Data refresh

365191, 365193, G11C 700

Patent

active

053216628

ABSTRACT:
An improved dynamic random access memory (DRAM) having self refresh mode is provided. After initiation of a self refresh term Ts, and in a first term Tc1 and a last term Tc2, a concentrated refresh using a refresh clock signal /REFS having a short period Pc is carried out for all rows in a memory cell array. During the remaining term, a normal self refresh operation using a signal /REFS having a long period Ps is carried out. Stored data is maintained effectively because the refresh interval of each row in a memory cell array is prevented from exceeding significantly a predetermined time length Ps.

REFERENCES:
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patent: 4933907 (1990-06-01), Kumanoya et al.
patent: 4935900 (1990-06-01), Ohsawa
patent: 5031147 (1991-07-01), Maruyama et al.
"Mitsubishi LSI's", pp. 1/28-10/28, 20/28, Oct. 1991.
Digest of Technical Papers, International Solid-State Circuits Conference, pp. 252-253, 1985 no month.

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