Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1993-04-12
1994-06-14
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Data refresh
365191, 365193, G11C 700
Patent
active
053216628
ABSTRACT:
An improved dynamic random access memory (DRAM) having self refresh mode is provided. After initiation of a self refresh term Ts, and in a first term Tc1 and a last term Tc2, a concentrated refresh using a refresh clock signal /REFS having a short period Pc is carried out for all rows in a memory cell array. During the remaining term, a normal self refresh operation using a signal /REFS having a long period Ps is carried out. Stored data is maintained effectively because the refresh interval of each row in a memory cell array is prevented from exceeding significantly a predetermined time length Ps.
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Glembocki Christopher R.
LaRoche Eugene R.
Mitsubishi Denki & Kabushiki Kaisha
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