Dynamic random access memory device and operating method therefo

Details Dynamic random access memory device and operating method therefo Dynamic random access memory device and operating method therefo

1988-10-20

1990-04-10

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365149, 365205, G11C 700

Patent

active

049166662

ABSTRACT:
In a DRAM device in accordance with the present invention, when a memory cell is selected for reading or writing data, at least one of the bit lines adjacent to the bit lines related with the selected memory cell is not selected simultaneously. Consequently, loss in a sense margin due to capacitance coupling between adjacent bit lines can be reduced.

REFERENCES:
patent: 4476547 (1984-10-01), Miyasaka
patent: 4748596 (1988-05-01), Ogura et al.

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