Dynamic random access memory device and operating method therefo

Details Dynamic random access memory device and operating method therefo Dynamic random access memory device and operating method therefo

1988-12-01

1990-06-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

36523003, G11C 1134

Patent

active

049339079

ABSTRACT:
A dynamic random access memory having a self-refresh mode comprises a memory array partitioned into four groups in which control are respectively performed and a partial activation control circuit. The four groups in the memory array are alternately refreshed two by two in an operation under the self-refresh mode. As a result, each group in the memory array is refreshed at a time interval of two times a conventional refresh interval, so that the power consumption is decreased.

REFERENCES:
patent: 4653030 (1987-03-01), Tachibana et al.
Shozo Saito et al., "A 1Mb CMOS DRAM with Fast Page and Static Column Modes" ISSCC 85, Feb. 15, 1985, pp. 252-253.
Michiro Yamada et al., "A 64Kbit Dynamic RAM with Auto/Self Refresh Functions". Electronics and Communications in Japan, vol. 66-C, No. 1, 1983, pp. 103-110.

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