Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-08-01
2001-10-30
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S206000, C365S001000
Reexamination Certificate
active
06310796
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Filed of the Invention
The present invention relates to a dynamic random access memory device, and more particularly to a dynamic random access memory device having a plurality of input receivers and a micro Ball Grid Array (hereinafter referred to as &mgr;BGA) package in which the device is embedded.
2. Description of the Prior Art
A rambus dynamic random access memory (DRAM) commonly includes a plurality of input receivers for transforming input data signals to voltage levels suitable for the operations in the rambus DRAM. Each input receiver generally includes a differential amplifying unit for generating output data signals according to a voltage difference between the corresponding input data signal and a reference voltage. Furthermore, the differential amplifying unit commonly includes a first NMOS transistor having a gate that receives the input data signal and a second NMOS transistor having a gate that receives the reference voltage. The gates of the first NMOS transistors in the input receivers respectively connect (one-to-one) to data input pads of the DRAM. All of the gates of the second NMOS transistors connect to a single reference voltage input pad.
Generally, the gates and drains of the transistors in the input receivers overlap to create parasitic capacitors. As a result, when a plurality of input receivers simultaneously operate, parasitic capacitors formed between the gates and drains of the second NMOS transistors capacitively couple the reference voltage to the output terminals of the differential amplifiers. Changes in the output signals from the differential amplifiers create noise in the reference voltage at the input receivers. If the parasitic capacitance is large, the reference voltage can fluctuate enough to cause false operations of the input receivers. Additionally, the input receivers further from the reference voltage input pad generally suffer from higher noise levels in the reference voltage. As the noise level in the reference voltage gets higher, those input receivers have greater differences in input characteristics and data set-up and hold times.
Accordingly, in the conventional rambus DRAM, an input receiver positioned far from the reference voltage input pad has higher noise levels and requires a greater margin in the data set-up and hold times to avoid false operation.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a DRAM device that minimizes the noise level in the reference voltage by using multiple reference voltage pads. Optionally, filtering elements can be coupled to the reference voltage pads to stabilize and reduce noise in the reference voltage. The DRAM device can be embedded in a &mgr;BGA package having a single ball coupled to the multiple reference voltage pads.
An exemplary embodiment of the present invention is a DRAM device including n input receivers, n data input pads, and x reference voltage pads, where x is greater than one but less than n. Each input receiver includes a differential amplifying unit that generates an output data signal according to a voltage difference between an input data signal and a reference voltage. The input receivers are synchronized with a clock signal and are divided into x groups according to their positions. The data input pads respectively connect to corresponding input receivers and relay corresponding input data signals to the corresponding input receivers. Each reference voltage input pad connects to a corresponding group of input receivers and commonly applies the reference voltage to the input receivers in the corresponding group.
In another exemplary embodiment of the invention, a &mgr;BGA package includes a plurality of balls electrically connect to the input receivers in a DRAM device. The DRAM device has n input receivers, n data input pads, and x voltage reference pads. The n input receivers are divided into x groups. Each input receiver has a differential amplifying unit, which generates an output data signal according to the voltage difference between an input data signal and a reference voltage. The input receivers are synchronized with a clock signal and divided into x groups according to their positions. The n data input pads respectively connect to corresponding input receivers, and each input pad relays an input data signal to the corresponding input receiver. The balls electrically connect to the data input pads and the reference voltage input pads. A ball to which the external reference voltage is applied is commonly connected to the x reference voltage input pads.
REFERENCES:
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patent: 5880987 (1999-03-01), Merritt
patent: 5886917 (1999-03-01), Yasukawa et al.
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patent: 6069814 (2000-05-01), Liou et al.
patent: 6088253 (2000-07-01), Shimizu
Heid David W.
Nguyen Tan T.
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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