Dynamic random access memory device and method for...

Details Dynamic random access memory device and method for... Dynamic random access memory device and method for...

Filed on

2008-05-06

Date issued

2008-05-06

Examiner

Dinh, Son (Department: 2824)

Patent Class

Static information storage and retrieval

SubClass

Read/write circuit

SubSubClass

Data refresh

Other Related Categories

C365S189050

Type

Reexamination Certificate

Status

active

Patent number

07369451

Description

ABSTRACT:
A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal. In response to the oscillation signal, a self-request controller provides a self-refresh request signal in the self-refresh mode. The self-refresh signal is asynchoronized with the self-fresh mode signal and is provided to an address circuit to select a wordline for refreshing the memory cells thereof. The self-refresh request controller includes logic circuitry for arbitrating timing between initial active edges of the oscillation signal and the self-refresh mode signal and providing the self-refresh request and ceasing it, regardless of conflict between the self-refresh mode signal and the oscillation signal upon self-refresh mode entry and exit. The DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.

REFERENCES:
patent: 4636989 (1987-01-01), Ikuzaki
patent: 5365487 (1994-11-01), Patel et al.
patent: 5566117 (1996-10-01), Okamura et al.
patent: 5862093 (1999-01-01), Sakakibara
patent: 6741515 (2004-05-01), Lazar et al.
patent: 6922369 (2005-07-01), Kim
patent: 7286377 (2007-10-01), Pyeon

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