Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2011-03-15
2011-03-15
Dinh, Son (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189050, C365S189080
Reexamination Certificate
active
07907464
ABSTRACT:
A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal. In response to the oscillation signal, a self-request controller provides a self-refresh request signal in the self-refresh mode. The self-refresh signal is asynchoronized with the self-fresh mode signal and is provided to an address circuit to select a wordline for refreshing the memory cells thereof. The self-refresh request controller includes logic circuitry for arbitrating timing between initial active edges of the oscillation signal and the self-refresh mode signal and providing the self-refresh request and ceasing it, regardless of conflict between the self-refresh mode signal and the oscillation signal upon self-refresh mode entry and exit. The DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.
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U.S. Appl. No. 12/038,855 Notice of Allowance dated May 18, 2009.
Borden Ladner Gervais LLP
Dinh Son
Hung Shin
Mosaid Technologies Incorporated
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