Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1993-01-29
1995-04-11
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Data refresh
3241581, 365200, 365201, 371 102, G11C 700
Patent
active
054065224
ABSTRACT:
DRAM devices embodying the present invention have longer potential effective values of refresh interval. A self-refresh interval signal may be set in association with its refresh interval to minimize power consumption during the self-refresh operation mode. An inspection method may pick up DRAM devices with efficiency and without deterioration of yields. When self-refresh interval control signal SELFS assumes the logic level "H" to turn P channel type MOS transistor Qp off and N channel type MOS transistor Qn on, the node N14 is brought to ground voltage VSS. The P channel type MOS transistor Qp and the N channel type MOS transistor Qn determine the time constant at which oscillation is generated. The oscillation output is applied to memory cells of the DRAM devices to enable the self-refresh mode of operation.
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Glembocki Christopher R.
LaRoche Eugene R.
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