Dynamic random access memory device

Details Dynamic random access memory device Dynamic random access memory device

1998-10-13

2001-01-23

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S297000, C257S369000, C257S390000, C257S401000

Reexamination Certificate

active

06177694

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memories, and, more particularly, to dynamic random access memories (DRAMs).
BACKGROUND OF THE INVENTION
Unlike static random access memories (SRAMs) in which the information stored remains so indefinitely at least as long as these memories remain energized, dynamic memories have the particular feature of requiring periodic refreshing of the information stored because of the stray leakage currents which discharge the storage capacitor of each memory cell (memory slot). This refreshing is conventionally performed in the course of a read/re-write cycle consequently requiring a specific phase for re-writing the data read.
Among the known memory cells for dynamic random access memories, mention may be made in particular of those containing two or three transistors, and those containing a single transistor, the information in which is moreover destroyed by reading.
SUMMARY OF THE INVENTION
An object of the invention is to provide a radically different structure of a memory cell of a dynamic random access memory allowing, in particular, automatic refreshing of the data read—this automatic refreshing, therefore, not requiring any specific re-write phase. Moreover, the reading of data from the memory cell according to the invention does not destroy this data.
Another object of the invention is also to propose a memory structure in which the area occupied by the circuits required to read/write the memory plane (“overhead”) is less than that of the corresponding circuits associated with known dynamic random access memories.
Yet another object of the invention is to propose a memory structure which uses a smaller number of metallization levels, thus decreasing the probability of a structural defect.
The invention therefore proposes a dynamic random access memory device comprising memory cells organized in rows and columns, and in which each memory cell comprises four insulated-gate field-effect transistors. These four transistors are made up of two storage transistors and two access transistors. The two storage transistors both possess the same quotient or ratio of their channel width W1 to their channel length L1, and the two access transistors both possess the same quotient or ratio of their channel width W2 to their channel length L2. The ratio of the first quotient W1/L1 to the second quotient W2/L2 is greater than or equal to 1 and, preferably greater than or equal to 2.
As will be seen in greater detail below, the memory cell with four transistors according to the invention can be “refreshed”, read or written. However, in fact, the refresh is performed at the start of the read cycle so that the memory cell is automatically refreshed when it is read. Now, in the course of this operation, a voltage spike appears on the side of the node which had been taken to zero potential during writing. Additionally, if this voltage spike is too large, the memory cell may lose its data, refresh in the wrong direction and ultimately read out erroneous data. Choosing the above mentioned ratio of the two quotients W/L makes it possible to avoid such a malfunction.
According to one embodiment of the invention, each memory cell comprises a first input and a second input for respectively receiving, during the read and write phases, two control voltages (corresponding to the voltages applied to a first column metallization or “bit line” and to an immediately adjacent reference column metallization). Each memory cell also comprises a selection input for receiving a row selection voltage conveyed by a specific row metallization (“wordline”). Furthermore, the source of a first access transistor is connected to the first input, while the source of the second access transistor is connected to the second input. The drain of the first access transistor is connected to the drain of a first storage transistor and to the gate of the second storage transistor, while the drain of the second access transistor is connected to the drain of the second storage transistor and to the gate of the first storage transistor. The sources of the two storage transistors are together connected to a first bias voltage (for example, ground in the case of NMOS transistors or else the high voltage level VDD in the case of PMOS transistors). Lastly, the gates of the two access transistors are connected to the selection input and consequently to the wordline. The four transistors may be NMOS transistors or PMOS transistors.
To reduce the leakage currents especially through the drain-source path of the storage transistors, and hence to improve the retention time of the stored data, it is possible to bias the substrate of all the transistors suitably so as to obtain, using the “substrate effect”, an increase in the threshold voltage and consequently an increase in retention time. Within the meaning of the invention, the term “substrate” (or “bulk”) denotes the substrate proper when the transistor is not placed in a well, or indeed the well if there is one. More precisely, in the case of NMOS transistors, the well will advantageously be biased negatively, while in the case of PMOS transistors the well will advantageously be biased to a voltage greater than the voltage VDD.
More generally, the substrates of all the transistors are preferably connected to a second predetermined bias voltage, and the first and second bias voltages are chosen so that the difference between the second bias voltage and the first bias voltage is negative or zero in the case of NMOS transistors, while remaining greater than the additive inverse of the threshold voltage of the transistors. In the case of PMOS transistors, the difference between the second bias voltage and the first bias voltage is chosen to be positive or zero, while remaining less than the sum of the first bias voltage and the threshold voltage of the transistors.


REFERENCES:
patent: 4023149 (1977-05-01), Bormann et al.
patent: 0681331A (1995-11-01), None

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