Dynamic random access memory controller

Details Dynamic random access memory controller Dynamic random access memory controller

2007-01-23

2007-01-23

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S157000

Reexamination Certificate

active

10458049

ABSTRACT:
An apparatus, and method and computer program thereof, comprises a plurality of ports each adapted to receive packets of data; a memory controller core adapted to generate one or more memory transactions for each of the packets of the data, wherein each memory transaction comprises a payload having a size of m bytes, and wherein the payloads contain the data; a memory comprising a plurality of memory banks adapted to store the data, wherein the memory can receive no more than n bytes of data in a single memory transaction; and a memory interface adapted to transmit the memory transactions to the memory; wherein m=kn and k is an integer.

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patent: 6418063 (2002-07-01), Seitsinger et al.
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