Dynamic random access memory circuit having a testing system and

Details Dynamic random access memory circuit having a testing system and Dynamic random access memory circuit having a testing system and

1999-04-07

2000-05-23

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

365210, G11C 700, G11C 702

Patent

active

060672633

ABSTRACT:
A dynamic random access memory (DRAM) circuit is provided that utilizes a testing system and method to determine the sensitivity of a sense amplifier. More specifically, the DRAM circuit, in determining the sensitivity of the sense amplifier, utilizes a testing system to independently control the magnitude of a voltage differential appearing between a pair of bit lines and sensed by the sense amplifier. The sensitivity of the sense amplifier is then able to be determined by monitoring an input/output signal in response to sensing the known voltage differential. The testing system controls the magnitude of the voltage differential appearing between the bit lines by enabling a first dummy cell to transfer a first reference charge onto a first bit line and by enabling a second dummy cell to transfer a second reference charge onto a second bit line.

REFERENCES:
patent: 5361232 (1994-11-01), Petschauer et al.
patent: 5428574 (1995-06-01), Kuo et al.
patent: 5532963 (1996-07-01), Kushiyama et al.

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