Dynamic random access memory cells having laterally offset...

Details Dynamic random access memory cells having laterally offset... Dynamic random access memory cells having laterally offset...

2006-10-10

2006-10-10

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S202000, C257S207000, C257S208000, C257S027000, C257S021000, C257S027000

Reexamination Certificate

active

07119389

ABSTRACT:
DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions. First and second storage nodes are provided on the integrated circuit substrate, a respective one of which is electrically connected to a respective one of the first and second source regions. The first and second storage nodes are laterally offset from the respective first and second source regions along the first direction.

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Notice to File A Response/Amendment to the Examination Report, KR Patent Application No. 2003-0039386, Aug. 31, 2004.
Translation of an Official Letter as issued by the German Patent and Trademark Office, Official File No. 10330072.4-33, Dec. 1, 2004.

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