Dynamic random access memory cell suitable for integration with

Details Dynamic random access memory cell suitable for integration with Dynamic random access memory cell suitable for integration with

1998-12-22

2000-08-01

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257532, H01L 27108

Patent

active

060970480

ABSTRACT:
A dynamic random access memory (DRAM) cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors functions as a switch transistor while the other transistor is configured as a storage capacitor. The DRAM cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the DRAM cell may be fabricated in a logic device with the standard processes used to produce the logic device.

REFERENCES:
patent: 5282159 (1994-01-01), Ueda et al.
patent: 5949706 (1999-09-01), Chang et al.

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