Dynamic random access memory cell leakage current detector

Details Dynamic random access memory cell leakage current detector Dynamic random access memory cell leakage current detector

2006-04-25

2006-04-25

Phan, Trong (Department: 2827)

Static information storage and retrieval

Systems using particular element

Capacitors

Reexamination Certificate

active

07035131

ABSTRACT:
A circuit operable to measure leakage current in a Dynamic Random Access Memory (DRAM) is provided comprising a plurality of DRAM bit cell access transistors coupled to a common bit line, a common word line, and a common storage node, wherein said access transistors may be biased to simulate a corresponding plurality of inactive bit cells of a DRAM; and a current mirror in communication with the common storage node operable to mirror a total leakage current from said plurality of bit cell access transistors when the access transistors are biased to simulate the inactive bit cells.

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