Dynamic random access memory cell having a stacked capacitor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257296, 257311, H01L 27108, H01L 2994

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active

055720536

ABSTRACT:
A DRAM device includes bit lines formed on an interlayer insulation film which covers gate electrodes on an insulation film on a semiconductor substrate. Each bit line is in contact with the corresponding source region formed in the substrate through an opening in the insulation films. Another insulation film is formed so as to cover the bit lines. A storage electrode is formed on the insulation film covering the bit line, and is in contact with a drain region in the substrate through another opening in the insulation films. The bit line has a vertical layer level lower than that of the storage electrode. The storage electrode is covered with a dielectric film, which is covered with an opposed electrode.

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Shah et al; A 4-Mbit DRAM with Trench-Transistor Cell; IEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1980.
Patent Abstracts of Japan, vol. 11, No. 376 (E-563) (2823), Dec. 8, 1987; JP-A-62 145 765 (Hitachi Ltd.).
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IEEE Journal of Solid-State Circuits, vol. SC-15, No. 4, Aug. 1980, "A 5-V Only 16-Kbit Stacked-Capacitor MOS RAM", M. Koyanagi et al., pp. 661-666.

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