Dynamic random access memory cell having a charge amplifier

Details Dynamic random access memory cell having a charge amplifier Dynamic random access memory cell having a charge amplifier

1985-07-26

1987-06-30

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Capacitors

365177, G11C 1124

Patent

active

046775897

ABSTRACT:
An improved dynamic random access memory (DRAM) cell circuit (46) having a charge amplifier is presented. The improvement comprises a bipolar amplification means (64) for amplifying a charge as it is read out of the memory cell (46). According to one embodiment of the present invention, in addition to a standard charge storage capacitor (50) and MOS transistor (48), the memory cell (46) also includes a write control line (60) and a second MOS transistor (62) for writing a "1" bit of information into the memory cell (46). These improvements require little or no additional space when used in a DRAM circuit and allow a reduction in the required capacitor area.

REFERENCES:
patent: 3745539 (1973-07-01), Davidson et al.
patent: 4168536 (1979-09-01), Joshi et al.
R. A. Carballo et al., "High Performance/Density Dynamic RAM Cell", IBM Technical Disclosure Bulletin, vol. 26, No. 7A, Dec. 1983, pp. 3227-3228.
Chung-Yu Wu, "A New Dynamic Random Access Memory Cell Using a Bipolar MOS Composite Structure", IEEE Transactions on Electron Devices, vol. ED-30, No. 8, Aug. 1983, pp. 886-894.

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