Dynamic random access memory cell and method for fabricating the

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257305, 257401, 257751, 257754, 257908, 257909, 437 48, 437 50, 437186, 437203, 437233, 437913, H01L 27108, H01L 21265

Patent

active

055005446

ABSTRACT:
The DRAM cell comprises a bit line having a topology higher than a plate electrode atop a dielectric film formed on a charge storage electrode, wherein the bit line is connected with a drain region and also with an oxide film which is formed at a predetermined portion of the plate electrode placed above the drain region, the oxide film playing a role in insulating said plate electrode from said bit line.
Serving as an insulator between the plate electrode and the bit line, the oxide film is formed by oxidizing the plate electrode adjacent to the bit line. By virtue of this oxide film, there can be secured allowance for the formation of highly integrated device.
A DRAM cell can be fabricated in fewer process steps according to the present invention. The DRAM cell is superior in reliability even if it is highly integrated since the area of the capacitor is largely secured without any short phenomenon of bit line.

REFERENCES:
patent: 5109259 (1992-04-01), Banerjee
patent: 5264712 (1993-11-01), Murata

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