Dynamic random access memory cell and method for fabricating the

Static information storage and retrieval – Systems using particular element – Semiconductive

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36518515, 36518528, G11C 1300

Patent

active

060882603

ABSTRACT:
A dynamic random access memory(DRAM) cell having no capacitor, comprising: a silicon layer doped with impurities of a first conductivity type; a metal oxide semiconductor (MOS) transistor having a gate formed on one surface of the silicon layer and a source and drain regions formed in the silicon layer, the source and the drain regions being doped with impurities of a second conductivity type to induce channel in the silicon layer under the gate; an insulating layer formed on another surface of the silicon layer; a conduction layer for a plate electrode formed on the insulating layer; and a purge region formed in the silicon layer to purge minor carriers induced in an interface surface between the silicon layer and the insulating layer, the purge region doped with impurities of the first conductivity type.

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patent: 5047356 (1991-09-01), Li et al.
patent: 5246870 (1993-09-01), Merchant
patent: 5363325 (1994-11-01), Sunouchi et al.
patent: 5663085 (1997-09-01), Tanigawa
patent: 5710451 (1998-01-01), Merchant
patent: 5780900 (1998-07-01), Suzuki et al.

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