Dynamic random access memory cell

Details Dynamic random access memory cell Dynamic random access memory cell

1993-09-08

1994-10-18

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257303, 257306, H01L 2968, H01L 2978, H01L 2992

Patent

active

053571320

ABSTRACT:
A memory for a dynamic random access memory includes an isolation trench formed between a pair of cells. Pass gate transistors are formed on either side of the isolation trench, with source/drain regions for contacting to a bit line formed on the opposite side of a gate electrode from the isolation trench. A source/drain region for each transistor is formed between the gate electrode and the isolation trench, and is used for a charge storage capacitor connection. For each transistor, a conductive plug is formed in contact with the capacitor source/drain region and extending vertically above this region and the gate electrode. This conductive plug forms the charge storage node of the capacitor, and is covered by a dielectric layer and a common capacitor reference plate.

REFERENCES:
patent: 4495219 (1985-01-01), Kato et al.
patent: 4743953 (1988-05-01), Toyokura et al.
patent: 4797719 (1989-01-01), Ueda
patent: 4918499 (1990-04-01), Matsutani et al.
patent: 5136533 (1992-08-01), Harari
Ohta et al., "Quadruply Self-Aligned Stacked High-Capacitance RAM Using Ta.sub.2 O.sub.5 High-Density VLSI Dynamic Memory", IEEE Transactions on Electron Devices, vol. ED. 29 No. 3, Mar. 1982.
Koyanagi et al., "A 5-V Only 16-Kbit Stacked Capacitor MOSRAM", IEEE Transactions Electron Devices, vol. ED 27, No. 8, Aug. 1980.

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