Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
1997-12-19
2002-11-05
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S208000, C365S190000, C365S149000, C365S063000
Reexamination Certificate
active
06477098
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to dynamic random access memories, and more specifically to a dynamic random access memory array in which digit lines are segmented to thereby decrease the capacitance of such digit lines.
BACKGROUND OF THE INVENTION
In a conventional dynamic random access memory (DRAM), a memory-cell array includes a number of memory cells arranged in rows and columns. Each memory cell in a particular row has an access terminal coupled to an associated word line, and each memory cell in a particular column has a data terminal coupled to one of an associated pair of complementary digit lines. Typically, an individual memory cell includes a single storage capacitor, and data is stored in the cell in the form of charge on the storage capacitor. The DRAM further includes a number of sense amplifiers, each sense amplifier typically coupled through a pair of isolation devices to the complementary digit lines associated with a respective column of memory cells. As known in the art, the sense amplifiers operate to sense a voltage differential on the associated pair of complementary digit lines and to drive the digit lines to voltage levels corresponding to complementary logic levels in response to the sensed voltage differential. Thus, the sense amplifiers are used to sense and store data contained in addressed memory cells during a read data transfer operation.
During a read data transfer operation, all of the digit lines in the memory-cell array are biased and equilibrated, typically to a voltage equal to one-half of the supply voltage V
CC
. Once the digit lines have been biased and equilibrated, a row address is decoded and the word line corresponding to the decoded row address is activated. In response to the activated word line, each memory cell coupled to that word line transfers the charge stored on the associated storage capacitor to the associated one of the pair of complementary digit lines. This transfer of charge results in the voltage on the digit line either slightly increasing or slightly decreasing relative to the biased and equilibrated voltage of V
CC
/2. As a result, one digit line in each pair of complementary digit lines now has a voltage equal to V
CC
/2 while the other digit line in the pair has a voltage slightly less than or greater than this value. The sense amplifier coupled to each complementary pair of digit lines senses this voltage differential and drives the digit line having the lesser voltage to ground and the digit line having the greater voltage to approximately the supply voltage. In this way, the sense amplifiers operate to sense the data stored in each memory cell in an activated row in the memory-cell array.
The voltage differential that must be sensed by each sense amplifier is typically very small, on the order of several hundred millivolts. In order to reliably sense such a small voltage differential, the components of the sense amplifier must be formed according to precise manufacturing tolerances, which increases the cost of fabricating the DRAM. The reason the voltage differential is so small is that the capacitance of each digit line is much greater than the capacitance of the storage capacitor of each memory cell. As a result, the charge transferred from the storage capacitor in the memory cell to the digit line does not result in a significant increase or decrease in the voltage of the digit line. One way to increase the voltage differential between the complementary pair of digit lines is to increase the value of the storage capacitor in the memory cell, or, conversely, to decrease the capacitance of the digit lines. Both alternatives, however, are difficult to implement. The capacitance of the storage capacitor in each memory cell, if increased, results in a larger memory cell resulting in fewer memory cells fabricated on the same size semiconductor substrate. Similarly, the digit lines must be formed in the semiconductor substrate having particular dimensions to satisfy particular design criteria, and variations in the layout and dimensions of the digit lines to decrease the capacitance of the digit lines may be contrary to the required design criteria.
There is a need for a DRAM capable of providing an increased voltage differential on digit lines in response to activated memory cells in a memory-cell array.
SUMMARY OF THE INVENTION
A dynamic random access memory device includes dynamic cell plate sensing of data stored in memory cells in the memory device. The memory device comprises a number of first and second digit line portions, each of which is formed from a first conductive layer on a substrate. The memory device also includes a number of strap portions, each of which is formed from a second conductive layer on the substrate. A number of cell plates are formed from a third conductive layer on the substrate, each of which receives a reference voltage. A number of memory cells are arranged in rows and columns. Each memory cell in a row includes an access terminal coupled to an associated word line. Each memory cell in a column has a data terminal coupled to one of the first and second digit line portions associated with the column.
A number of sense amplifiers are contained in the memory device, each of which is associated with a column of memory cells. Each sense amplifier has first and second data terminals. Each sense amplifier is operable to sense a voltage differential between the data terminals and drive the data terminals to voltage levels corresponding to complementary logic levels in response to the sensed voltage differential. A number of first isolation devices, each having a control terminal coupled to receive a first control signal, a first signal terminal coupled to the first terminal of an associated sense amplifier, and a second signal terminal coupled to an associated first digit line portion, are each operable to couple the first signal terminal to the second signal terminal in response to the first control signal. A number of second isolation devices, each having a control terminal coupled to receive a second control signal, a first signal terminal coupled to the first terminal of an associated sense amplifier, and a second signal terminal coupled through an associated strap portion to an associated second digit line portion, are each operable to couple the first signal terminal to the second signal terminal in response to the second control signal. A number of third isolation devices, each having a control terminal coupled to receive a third control signal, and first and second signal terminals coupled between the at least one cell plate and the second terminal of an associated sense amplifier, are each operable to couple the first signal terminal to the second signal terminal in response to the third control signal.
REFERENCES:
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patent: 5608668 (1997-03-01), Zagar et al.
patent: 5726931 (1998-03-01), Zagar et al.
patent: 5796666 (1998-08-01), Shirley et al.
patent: 5856939 (1999-01-01), Seyyedy
patent: 5862072 (1999-01-01), Raad et al.
patent: 5862089 (1999-01-01), Raad et al.
Micro)n Technology, Inc.
Phan Trong
Seed and Berry LLP
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